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| W42C31-06 Spread Spectrum Frequency Timing Generator Features * Maximized EMI suppression using Cypress's Spread Spectrum technology * Generates a spread spectrum 3X copy of the input * Integrated loop filter components * Operates with a 5V supply * Low-power CMOS design * Available in 8-pin SOIC (Small Outline Integrated Circuit) to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. Table 1. Frequency Spread Selection W42C31-06 FS0 0 1 Oscillator Input Frequency (MHz) 14 to 20 14 to 20 XTAL Input Frequency (MHz) 14 to 20 14 to 20 Output Frequency (MHz) 3fIN 0.75% 3fIN 1.25% Overview The W42C31-06 incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, EMI is greatly reduced. Use of this technology allows systems Simplified Block Diagram 5.0V Pin Configuration SOIC X1 XTAL Input W42C31-06 X2 W42C31-06 Spread Spectrum Output (EMI suppressed) X1 X2 GND FS0 1 2 3 4 8 7 6 5 SSON# NC VDD CLKOUT 5.0V Oscillator or Reference Input W42C31-06 Spread Spectrum Output (EMI suppressed) Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 September 29, 1999, rev. ** W42C31-06 Pin Definitions Pin Name CLKOUT X1 Pin No. 5 1 Pin Type O I Pin Description Output Modulated Frequency: Frequency modulated copy of the unmodulated input clock (multiplier of 3). Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. Crystal Connection: If using an external reference, this pin must be left unconnected. Spread Spectrum (Active LOW): Pulling this input signal HIGH turns the internal modulating waveform off. This pin has an internal pull-down resistor. Frequency Selection Bit 0: This pin selects the frequency spreading characteristics. Refer to Table 1. This pin has an internal pull-up resistor. No Connect: This pin must be left unconnected. Power Connection: Connected to 5V power supply. Ground Connection: This should be connected to the common ground plane. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed, the modulation percentage may be varied. Using the frequency select bit (FS0), the spreading percentage can be chosen (see Table 1). A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common. The W42C31 features the ability to select from various spread spectrum characteristics. Selections specific to the W42C31-06 are shown in Table 1. Other spreading characteristics are available (see separate data sheets) or can be created with a custom mask. X2 SSON# FS0 NC VDD GND 2 8 4 7 6 3 I I I NC P G Functional Description The W42C31-06 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. An on-chip crystal driver causes the crystal to oscillate at its fundamental. The resulting reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. The unique feature of the Spread Spectrum Clock Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. VDD X1 XTAL X2 Freq. Divider Q Phase Detector Charge Pump CLKOUT VCO Post Dividers Modulating Waveform Crystal load capacitors as needed Feedback Divider P PLL GND Figure 1. System Block Diagram 2 W42C31-06 Spread Spectrum Frequency Timing Generation The benefits of using Spread Spectrum Frequency Timing Generation are depicted in Figure 2. An EMI emission profile of a clock harmonic is shown. 5dB/div SSFTG Typical Clock Modulating Waveform The shape of the modulating waveform is critical to EMI reduction. The modulation scheme used to accomplish the maximum reduction in EMI is shown in Figure 3. The period of the modulation is shown as a percentage of the period length along the X axis. The amount that the frequency is varied is shown along the Y axis, also shown as a percentage of the total frequency spread. Cypress frequency selection tables express the modulation percentage in two ways. The first method displays the spreading frequency band as a percent of the programmed average output frequency, symmetric about the programmed average frequency. This method is always shown using the expression fCenter XMOD% in the frequency spread selection table. The second approach is to specify the maximum operating frequency and the spreading band as a percentage of this frequency. The output signal is swept from the lower edge of the band to the maximum frequency. The expression for this approach is fMAX - XMOD%. Whenever this expression is used, Cypress has taken care to ensure that fMAX will never be exceeded. This is important in applications where the clock drives components with tight maximum clock speed specifications. Amplitude (dB) Figure 2. Typical Clock and SSFTG Comparison SSON# Pin An internal pull-down resistor defaults the chip into spread spectrum mode. The SSON# pin enables the spreading feature when set LOW. When disabled (SSON# HIGH), the W42C31-06 simply passes through the input clock. Upon going LOW, the device takes 2 ms to re-track the spreading algorithm. 90% 100% 10% Contrast the typical clock EMI with the Cypress Spread Spectrum Frequency Timing Generation EMI. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With spread spectrum enabled, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth. 100% 80% 60% 40% 20% 0% -20% -40% -60% -80% -100% Frequency Shift 10% 20% 30% 40% 50% 60% 70% 80% 20% 30% 40% 50% 60% 70% 80% 90% Time Figure 3. Modulation Waveform Profile 3 100% W42C31-06 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD, VIN TSTG TA TB PD Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W DC Electrical Characteristics: 0C < TA < 70C, VDD = 5V 10% Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI CL RP ZOUT Description Supply Current Power Up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Load Capacitance (as seen by XTAL) Input Pull-Up Resistor Clock Output Impedance Note 1 Note 1 @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V All pins except X1, X2 Pins X1, X2 [2] Test Condition First locked clock cycle after Power Good Min Typ 20 Max 40 5 0.15VDD Unit mA ms V V V V A A mA mA 0.7VDD 0.4 2.5 -100 10 24 24 7 17 500 20 pF pF k AC Electrical Characteristics: TA = 0C to +70C, VDD = 5V10% Parameter fIN fOUT tR tF tOD tID tJCYC Description Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle Harmonic Reduction 8 Test Condition Input Clock Spread Off VDD, 15-pF load 0.8-2.4 VDD, 15-pF load 2.4-0.8 15-pF load 45 40 250 Min 14 42 2 2 Typ Max 20 60 5 5 55 60 300 Unit MHz MHz ns ns % % ps dB Notes: 1. Input FS0 has a pull-up resistor; Input SSON# has a pull-down resistor. 2. Pins X1 and X2 each have a 34-pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 17 pF. If driving X1 with a reference clock signal, the load capacitance will be 34 pF (typical). 4 W42C31-06 Application Information Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-F decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. W42C31-06 The 10-F decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. The 6-pF XTAL load capacitors can be used to raise the integrated 17-pF capacitance up to a total load of 20 pF on the crystal. Recommended Board Layout Figure 5 shows a recommended 2-layer board layout. 1 C1 6 pF XTAL1 8 7 6 5 R1 C3 0.1 F VDD Output 2 GND 3 4 C2 6 pF 5V System Supply FB C4 10 F Tantalum Figure 4. Recommended Circuit Configuration C1, C2 = XTAL load capacitors (optional; use is not required for operation). Typical value is 6 pF. High frequency supply decoupling capacitor (0.1-F recommended). Common supply low frequency decoupling capacitor (10-F tantalum recommended). Match value to line impedance Ferrite Bead Via To GND Plane Optional Guard Ring for XTAL Oscillator Circuitry C3 = C4 = G C1 R1 = FB = = G G C2 XTAL1 C3 G G R1 Clock Output G C4 Power Supply Input (5V) FB G Figure 5. Recommended Board Layout (2-Layer Board) Ordering Information Ordering Code W42C31 Document #: 38-00800 Freq. Mask Code 06 Package Name G Package Type 8-pin Plastic SOIC (150-mil) 5 W42C31-06 Package Diagram 8-Pin Small Outline Integrated Circuit (SOIC, 150-mil) (c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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